1. Field of the Invention
The invention relates to the etching of metal layers in combination or electrical contact with other metal layers. The invention also relates to particular etchant solutions used to etch metal layers, and particularly to etch aluminum layers in Galvanic contact with other metal layers. Articles formed from etched multiple metal layers may be used in electronic devices, and more particularly in circuitry or circuit boards. The invention is especially advantageous when applied to manufacturing processes for thin circuit boards, particularly circuit boards with multiple layers of individually prepared circuits. These circuit boards provide physically durable structures, even when including fragile microstructure such as air bridges.
2. Background of the Art
Metals have been conveniently etched to form complex designs, including circuitry, for many years. A mask or resist layer in the shape of a pattern to be removed from a metal layer is placed over a surface of the metal layer, a solution that dissolves or removes the metal is conracted with the mask on the surface of the metal layer, and because the soltuion can contact only the exposed metal through the mask directly, a pattern of metal is removed from the metal layer that corresponds to the pattern in the mask. Although the underlying technology for this process appears fairly simple and direct, there are many complications in the actual performance of the process. For example, the resist must provide good resolution for the image, the etchant solution must have properties so that it etches the metal along vertical lines rapidly, yet doesn""t undercut (etch along the side walls produced by the etching process), and with metal layers composites (elements having more than one metal layer, and layers of different metals) shoul be able to be etched one adjacent layer at-a-time, so that the solution does not etch completely through all of the layers. These are high performance standards that are not readily achieved,
A technique for forming a tri-layer metal structure is described in U.S. Pat. No. 5,428,250 to Ikeda et al. The tri-layer metal structure is formed on a glass substrate. The first layer is a Taxe2x80x94Mxe2x80x94N film, the second layer is a Ta film and the third (top) layer is a Taxe2x80x94Mxe2x80x94N film, where M is at least one atom selected from the group consisting of Molybdenum, Niobium, and Tungsten.
U.S. Pat. No. 5,153,754 to Whetten described a tri-layer metal structure formed on an LCD substrate where the first layer is a titanium (Ti) film, the second layer is a molybdenum (Mo) or aluminum (Al) film, and the third (top) layer is a titanium (Ti) film. In addition, colum 6, lines 56-70 describe a process to taper etch the tri-layer metal structure. When the second layer is a molybdenum film, the tri-layer structure is formed by wet etching the titanium first layer with fluoroboric acid (HBF4), wet etching the molybdenum second layer with PAWN (phosphoric acid, acetic acid, water and nitric acid), and dry etching the titanium third layer in a plasma barrel etcher with an atmosphere of CF4 and O2 (or SF6 and O2). When the second layer is an aluminum film, the tri-layer structure is formed in a single etch step by an RIE (reactive ion etching) etch of BCl3, CCl4 and O2.
U.S. Pat. No. 5,464,500 to Tsujimura et al. describes a tri-layer metal structure formed on a glass substrate. A silicon oxide layer is formed on the glass substrate. The first metal layer of Aluminum (Al) is formed on the silicon oxide layer. The second metal layer of aluminum oxide is formed on the first metal layer. The third metal layer of molybdenum is formed in the aluminum oxide layer. Beginning at column 3, line 60, a process for taper etching the tri-metal layer is described. As a result, the cross section of the first metal layer of aluminum is formed with a taper angle.
U.S. Pat. No. 4,824,803 to Us et al. describes a tri-layer metal structure formed on a glass layer wherein the first metal layer is a titanium (Ti) film, the second metal layer is an Aluminum (Al) film, and the third metal layer is a titanium film. As described beginning at column 2, line 45, the tri-metal structure is formed in a single RIE etch step of a chlorine based chemistry. As shown in FIGS. 1a and 1b, the RIE etch step results in a non-tapered structure with vertical sidewalls.
U.S. Pat. No. 4,650,543 teaches a GaAs FET electrode wiring layer or bonding pad having a three-layered structure of Au/Pt/Ti or a two-layered structure of Al/Ti. The electrode wiring layer or the bonding pad is sometimes formed by a wet etching method but mainly by a lift-off method. A method of forming a bonding pad by wet etching is described. In this case, an insulating film is formed on a GaAs semiconductor substrate by CVD, and thereafter a contact hole is selectively formed in the insulating film. A metal film for forming a bonding pad is deposited on the overall surface of the substrate, and a resist pattern is formed thereon. Finally, the metal film is etched by wet etching using the resist pattern as a mask so as to form a bonding pad of the metal film on the hole of the insulating film. In this method, since the GaAs semiconductor layer is highly sensitive to chemical treatment, when the wet etching method is used, side etching occurs. For this reason, this method is inappropriate for forming a micropattern such as a gate electrode. Note that in a GaAs FET, a submicron micropattern must be formed. Therefore, a lift-off method was developed for micropatterning. This method is described in U.S. Pat. No. No. 3,994,758. However, the metal film formed by this method was formed by CVD (Chemical Vapor Deposition) at a low temperature because of a resist film. For this reason, bonding between a metal multilayer and a semiconductor substrate constituting an electrode pattern was inadequate. Therefore, the electrode pattern was easily removed during lifting off or wire bonding, thus degrading the yield in manufacturing of the GaAs FET. This Patent asserted an advance in the technology by the electrode pattern having a multilayer structure selected from the group consisting of Au/WN, Au/W/TiW and Au/Mo/TiW (elements on the left side are positioned uppermost with respect to the semiconductor substrate). In an ion milling technique used in that invention, etching is performed by bombarding a member to be etched with ions of an inert gas such as Ar or At+O2 gas using a shower or beam type device. This technique is inert dry etching and is also called ion etching. This ion milling technique has been disclosed in, e.g., Solid State Tech. March 1983, Japanese Edition p. 51 to 62. In a reactive ion etching technique, by using a parallel-plate, microwave or ion-shower type device, dry etching is performed by reactive plasma using a reactive gas mixture such as CF4+O2 or CF4+Cl while activating a member to be etched using an inert gas such as Ar gas.
U.S. Pat. No. 5,912,506 addresses perceived problems of
(a) thinning of additional metal layers crossing the edges of the multi-layer metal structure;
(b) shorts or pinholes formed in one or more insulator layers above multi-layer metal structure due to near vertical or undercut edges; and
(c) controlling the effective width of the multi-layer structure when using an extended non-directional over-etch.
These problems are variously addressed by the invention of that Patent. A multi-layer metal sandwich structure formed on a substrate includes a first metal layer formed on the substrate and a second metal layer formed on the first metal layer. The second metal layer has tapered side walls. The width of the first metal layer is different than the width of the second metal layer at the interface of the first metal layer and the second metal layer. The multi-layer metal sandwich may also include a third metal layer formed on the second metal layer. The second metal layer may also be substantially thicker than the first or third metal layers. A method for forming the multi-layer metal sandwich with taper and reduced etch bias on a substrate includes the steps of forming a three-layer sandwich of metal on the substrate by forming a first metal layer on the substrate, forming a second metal layer on the first metal layer, and forming a third metal layer on the second metal layer. A resist pattern is formed on the three-layer sandwich, wherein the resist pattern defines etch areas in the three-layer sandwich. The etch areas are exposed to a first etchant that taper etches the second metal layer while not attacking the first metal layer. The etch areas are then etched using a directional etch process, which etches the first metal layer. The resist pattern in then removed. The third metal layer may be removed. Preferably, the first metal layer is titanium (or a titanium alloy), the second metal layer is Aluminum (or an Aluminum alloy), and the third metal layer is Molybdenum (or Molybdenum alloy) or Copper (or a Copper alloy) or other refractory metal (or alloy). In this case, the first etching process for taper etching the aluminum second layer utilizes a wet etchant that is a mixture of phosphoric acid, nitric acid, acetic acid, and water, and the second etching process for etching the titanium first metal layer utilizes an RIE etching process.
Each of these references emphasizes the fact that each multiple layer element has its own unique properties and tends to require unique processing solutions and processing controls. It is desirable to be able to provide different multi-layer sandwiches with unique properties, both within individual layers and within the functional ability of the composite. However, each such different system requires fundamental investigation of the properties and the processing necessities.
A significant manufacturing problem in every form of printed circuit manufacture is the assurance of appropriate registration of the circuitry, and especially the connect points, in the layers of circuits that are combined. Each different system of manufacture has its own unique complexities in attempting to obtain registration, and each manufacturing process requires its own specific type of controls and steps to provide good registration. For example, even in stacking circuits by etching layers in place, there can be significant registration problems. Some circuits boards are manufactured by stack etching individual layers of circuitry by providing a base layer with a first metal layer and first resist layer. The resist is imagewise exposed and the metal layer etched in correspondence to the pattern provided to form a first circuit. A second metal layer (with an insulating layer interposed between the etched first metal layer circuit and the second metal layer) is placed over the first etched circuit with a second resist on the exterior surface of the second metal layer. A second circuit layer is formed by imagewise exposure, development and etching of the second metal layer. This sequence of metal layer application, resist development and etching is repeated for each of the layers of circuitry required in the complete patterning and design of the circuit board. Through holes, pins or vias are used to connect contact points or leads of the circuitry of the individual layers of etched metal to the appropriate circuitry in other layers (either adjacent layers or in layers separated by other layers of circuitry). For the manufacturer to connect the circuit elements and contact points with straight line holes or pins, it is necessary that the contact points be aligned vertically. If the contact points are not aligned vertically through the stacked array of circuits in the circuit board, the electrical connectors passing through the layers may not make the required contact with the circuit elements and the circuit board will be partially non-functional. The smaller and finer the elements of the circuit board, the higher must be the resolution of the circuit elements and the higher must be the degree of alignment for the layers in the circuit board.
Many different features and phenomena in each of the processes add to the uncertainty of registration. For example, in forming the stacked arrays by stacking circuits and by etching layers in place, registration can be compromised by a) temperature changes occurring during processing causing layers to thermally expand and then contract, distorting the circuit image, b) physical mislaying of layers on top of each other, c) misalignment of the stack within the exposure area of a photoresist imaging systems, d) vibration shifting either the circuit element or the imaging element (e.g., the laser diode for the imaging of the resist), and the like. In the development of new systems and processes for the manufacture of circuit boards, the nature of registration problems must be addressed early in the development cycle or severe problems will be encountered during scale-up. Another likely cause of misregistration e) is a volume change in adhesives during curing or setting.
A process for the etching of multiple layers of at least two different metals comprisies:
forming a resist pattern over a first layer of metal, said resist pattern having a pattern of openings therein,
applying a first etch solution onto said resist pattern so that at least some etch solution contacts exposed areas of the first layer of metal,
etching away the majority of the depth of the first metal in exposed areas of metal in the first layer of metal,
applying a second etch solution onto the resist pattern the second etch solution having a rate of etch towards the first metal as compared to the first etch solution that is at least 20% less than the millimeter/minute rate of etch of the first etch solution at the same etch solution temperature,
removing the second etch solution from said resist pattern after at least the first metal layer has been etched sufficiently to expose areas of a second metal layer underlying the first metal layer by forming an etched first metal layer, and
applying a third etch solution to said etched first metal layer, the third etch solution having a fster rate of etch towards the second metal than towards the first metal to etch into said second metal layer without destroying theetched first metal layer.
The process may have the first and second etch solutions comprise at least one active ingredient in common between the two solutions, with the concentration of the common active ingredient being less than 75% the concentration in the second etch solution than in the first etch solution.
The process may have the second etch solution comprises a solution having a pH of at least 11.0 and an oxidizing agent. The process may have the second etch solution comprise a) an alkali metal hydroxide or an alkaline metal hydroxide and b) an oxidizing agent. A preferred process has the first metal layer comprise copper and the second metal layer comprise aluminum.
The process for the etching of at least connected metal layers may also have one layer comprise copper and another layer comprise aluminum, wherein the copper layer is etched with an acid solution and the aluminum layer is etched with a solution having a pH of at least 10.5 in the presence of an oxidizing agent. The process may have the oxidizing agent selected from the class consisting of metal salts of inorganic acids or organic acids, ferric salts of organic oxidizing acid, metal bromates, hydrogen peroxide, metal nitrates, metal nitrites, metal borates, metal phosphates, and ferricyanide salts.
A process allows the manufacture of circuitry from multi-layer metallic elements, the multi-layer metallic elements preferably comprising tri-metal subelements, such as copper/aluminum/copper sub-elements (hereinafter referred to as xe2x80x9ctri-metal sub-elements,xe2x80x9d even though more than three layers may be present) which are created, as by etching, to form individual sub-elements of circuits. These individual sub-elements of circuitry are formed by multiple-step processing (e.g., multiple layer plating up or multiple layer plating down, lamination, or preferably by etching of tri-metal sub-elements). Intermediate or completed circuits are formed by the lamination of the formed (e.g., etched or partially etched), tri-metal sub-elements to a base intermediate layer (support or ground plane, for example), and then electrically connecting the appropriate points of the circuitry through intermediate layers to form the circuit board. These individual sub-elements are then electrically connected (e.g., with any electrical connecting means known in the art, including but not limited to posts, vias or plated through-holes) to form larger circuit elements. Circuitry may be formed by any method including the following, not necessarily sequential, steps of a) providing a multiplicity of the (preferably, tri-metal) sub-elements, b) providing a separator sub-element between the (preferably) tri-metal sub-elements, c) drilling, plating, inserting posts, or coating through-holes to electrically connect at least two of the (preferably) tri-metal sub-elements, d) providing a resist layer on at least one surface of at least one of the (preferably) tri-metal sub-elements, e) exposing or otherwise activating the resist (e.g., exposing a radiation sensitive resist to appropriate radiation in an image-wise pattern, thermally exposing a thermal resist in an image-wise pattern, printing on a resist in an image-wise pattern, etc.), f) developing the resist pattern to expose an underlying surface of at least one (preferably tri-metal) sub-element (of course, one resist layer can expose only one underlying tri-metal sub-element at a time), g) etching at least one layer of the tri-metal sub-element through openings in the developed resist layer, and h) stripping the resist from the surface. After the first layer has been etched, the next layer (the preferably aluminum layer) may be etched, with the copper layer remaining as at least part of a resist surface. The remaining copper, after the second or third etch, may be coated with an organic solderability preservative (as that class of composition, often including rosin, is known in the art) or metallized, such as silvered to increase its solderability and/or conductivity. By this method, not only may conventional circuits be manufactured, but air bridges may also be constructed within the flow of process steps. The second exterior metal layer (e.g., the second copper layer) may be etched before or at the same time as the first metal layer (first copper layer), after the etching of the first layer but before etching of the interior aluminum layer, or after the etching of the first metal layer but after etching of the aluminum layer. Solder mask may be added at any of various stages of the process for the purpose of electrical insulation, underfilling of air bridges and encapsulation of cores, edges and traces, etc. Flexible, rigid, and segmented flexible and rigid (rigid-flex) circuit boards may be manufactured by the selection of appropriate layer thicknesses and support layer materials.
As the individual layers of circuit elements must be interconnected on the circuit board, it is desirable or even essential that a sufficient degree of registration is effected between each of the layers to be connected. This is difficult enough where only two (e.g., tri-metal) sub-elements are connected on opposite sides of a support, but the difficulty is magnified with more layers or when sheets of (preferably tri-metal) material are used from rolls or coils, and the lamination of the (e.g., etched tri-metal) sub-elements occurs in a continuous fashion. In the last process, misregistration can readily creep and increase in the layers as they are laminated due to the multiplying effect of slightly misregistered panels or circuits in coil or roll form. Rather than losing a single circuit board in that circumstance, an entire run of circuit boards could be lost. As part of the process of this invention, numerous points of registration can be integrated into the system by providing registration marks, using through holes as registration marks, optical feedback mechanisms, electrical connection checks during manufacture, registration marks in the original coils or rolls, registration marks added to the coils or rolls during the etching step, mechanical registration elements built or processed into the coils or rolls during processing or at the time of the original supply. Multiple numbers of etched tri-metal subelements also may be directly laminated together without intermediate supports or ground plane layers. This would be accomplished by applying adhesive to an outer surface (or remaining outer surface) of the etched tri-metal subelements. The adhesive would be a dielectric for best performance of the bonded multiple tri-metal subelements without an intervening distinct layer.